VGA/EGA emulation is hard because IBM’s documentation describes usage patterns, not what individual bits actually do, leaving implementors guessing.
Key Takeaways
Three separate Odd/Even bits (SR4[2], GR5[4], GR6[1]) control CPU writes, CPU reads, and addressing independently, but IBM’s TRM describes them only as a unit.
Compaq’s EGA Technical Reference Guide clearly separates SR4[2] (write plane select) from GR5[4] (read plane select) and GR6[1] (address bit routing), which IBM never does.
Matrox MGA-1064 docs reveal GR6[1] replaces CPU A0 with either system address A16 or MSR[5] (page select), depending on GR6[3:2] memory map selection bits.
MSR[5] polarity is contradicted across vendors: Matrox says 1 selects high page; ATI 264VT and Cirrus Logic Alpine say 1 selects low page.
CRTC has a completely separate set of addressing bits (CRTC14[6], CRTC17[0-1,5-6]) governing display refresh, independent of the CPU access bits above.
Hacker News Comment Review
Commenters clarify that VGA is planar internally even in Mode 13h: four chained 64KB planes underlie all modes, and “consecutive” pixel writes go to separate planes, not adjacent addresses.
The MCGA’s historical rarity versus the ubiquity of its 256-color mode is noted as a surprising legacy quirk with no deeper resolution in the thread.
